In fabricating integrated circuits, isolation regions are generally formed between active device regions to electrically isolate the regions from one another. One widely used isolation method is LOCal Oxidation of Silicon (LOCOS). Unfortunately, LOCOS isolation may create bird's beaks due to lateral oxidation, crystal defects in the integrated circuit substrates and/or redistribution of dopants that are ion implanted for channel stops. These and other disadvantages may make LOCOS isolation undesirable for high density integrated circuits.
Shallow Trench Isolation (STI) methods are also used to form isolation regions. In shallow trench isolation methods, an integrated circuit substrate is etched to form a trench and an insulating material is filled in the trench. Chemical-Mechanical Polishing (CMP) is then performed for form an insulation-filled trench. Since the shallow trench isolation method does not depend on a thermal oxidation process, at least some of the disadvantages of the LOCOS method can be avoided. Moreover, since narrow trenches may be formed in an integrated circuit substrate, high density integrated circuits may be formed.
Unfortunately, in shallow trench isolation methods, the insulating material is generally etched using chemical-mechanical polishing. The chemical-mechanical polishing may cause dishing in the middle of the trench, thereby recessing the trench surface. The recessed trench surface may degrade the isolation characteristics of the trench, and may also result in poor planarization of local regions.